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february 2012 doc id 022218 rev 1 1/35 35 VIPER37 viperplus family: fixed frequency offline converter features 800 v avalanche rugged power section pwm operation with adjustable limiting current 30 mw standby power at 265 vac operating frequency: ? 60 khz for l type ? 115 khz for h type frequency jittering for low emc output overvoltage protection high primary current protection (2 nd ocp) input undervoltage setting (brownout) onboard soft-start safe auto-restart after a fault condition hysteretic thermal shutdown applications smps for set-top boxes, dvd players and recorders, white goods auxiliary power supply for consumer and home equipment atx auxiliary power supply low / medium power ac-dc adapters description this device is an offline converter with an 800 v rugged power section, a pwm control, two levels of overcurrent protection, overvoltage and overload protection, hysteretic thermal protection, soft-start, and safe auto-restart after the removal of any fault condition. burst mode operation and very low device consumption help to meet the standby energy saving regulations. advance frequency jittering reduces emi filter costs. brownout function protects the switch mode power supply when the rectified input voltage level is below the normal minimum level specified for the system. the high voltage startup circuit is embedded in the device. figure 1. typical topology sdip10 dc input high voltage wide range + dc output voltage - + VIPER37 drain drain drain drain drain br vdd cont fb gnd table 1. device summary order codes package packaging VIPER37le sdip10 tube VIPER37he www.st.com
contents VIPER37 2/35 doc id 022218 rev 1 contents 1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 typical power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3 pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 4 electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 4.1 maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 4.2 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 4.3 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 5 typical electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 6 typical circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 7 efficiency performances for a typical flyback converter . . . . . . . . . . . 16 8 operation description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 8.1 power section and gate driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 8.2 high voltage startup generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 8.3 power-up and soft-start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 8.4 power down operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 8.5 auto-restart operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 8.6 oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 8.7 current mode conversion with adjustable current limit set point . . . . . . . 22 8.8 overvoltage protection (ovp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 8.9 about the cont pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 8.10 feedback and overload protection (olp) . . . . . . . . . . . . . . . . . . . . . . . . . 25 8.11 burst mode operation at no load or very light load . . . . . . . . . . . . . . . . . . 27 8.12 brownout protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 8.13 2nd level overcurrent protection and hiccup mode . . . . . . . . . . . . . . . . . . 30
VIPER37 contents doc id 022218 rev 1 3/35 9 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 10 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
block diagram VIPER37 4/35 doc id 022218 rev 1 1 block diagram 2 typical power figure 2. block diagram vdd th er mal shutdown 6ua leb & ovp logic soft start ocp block ref tu r n -on logic drain supply & uvlo otp olp burst internal supply bus br burst-mode logic burst s r1 r2 q + - uvlo vin_ok + - ocp ref erence voltages ovp 15ua istart-up ovp vcc oscillator fb v brth hv_on otp . gnd + - rsense cont + - pwm 2nd ocp logic vdd table 2. typical power part number 230 v ac 85-265 v ac adapter (1) open frame (2) adapter (1) open frame (2) VIPER37 23 w 25 w 13 w 15 w 1. typical continuous power in non-vent ilated enclosed adapter measured at 50 c ambient. 2. maximum practical continuous pow er in an open frame design at 50 c ambient, with adequate heatsinking.
VIPER37 pin settings doc id 022218 rev 1 5/35 3 pin settings figure 3. connection diagram (top view) note: the copper area for heat dissipation must be designed under the drain pins. "2 &" #/.4 6$$ '.$ $2!). $2!). $2!). $2!). $2!). table 3. pin description pin n. name function 1 gnd this pin represents the device ground and the source of the power section. 2vdd supply voltage of the control section. this pin also provides the charging current of the external capacitor during startup time. 3cont control pin. the following functions can be selected: 1. current limit set point adjustment. the internal set default value of the cycle-by- cycle current limit can be reduced by connecting to ground an external resistor. 2. output voltage monitoring. a voltage exceeding the v ovp threshold (see ta bl e 8 ) shuts the ic down reducing the device consumption. this function is stropped and digitally filtered for high noise immunity. 4fb control input for duty cycle control. internal current generator provides bias current for loop regulation. a voltage below the threshold v fbbm activates the burst mode operation. a level close to the threshold v fblin means that we are approaching the cycle-by-cycle overcurrent set point. 5br brownout protection input with hysteresis. a voltage below the threshold v brth shuts down (not latched) the device and lowers the power consumption. device operation restarts as the voltage exceeds the threshold v brth + v brhyst . it can be connected to ground when not used. 6...10 drain high voltage drain pin. the built-in high voltage switched startup bias current is drawn from this pin too. pins connected to the metal frame to facilitate heat dissipation.
electrical data VIPER37 6/35 doc id 022218 rev 1 4 electrical data 4.1 maximum ratings 4.2 thermal data table 4. absolute maximum ratings symbol parameter value unit min. max. v drain drain-to-source (ground) voltage 800 v e av repetitive avalanche energy (limited by t j = 150 c) 5mj i ar repetitive avalanche current (limited by t j = 150 c) 1.5 a i drain pulse drain current 3 a v cont control input pin voltage -0.3 6 v v fb feedback voltage -0.3 5.5 v v br brownout input pin voltage -0.3 5 v v dd supply voltage (i dd = 25 ma) -0.3 self limited v i dd input current 25 ma p tot power dissipation at t a < 60 c 1.5 w t j operating junction temperature range -40 150 c t stg storage temperature -55 150 c table 5. thermal data symbol parameter max. value unit r thjp thermal resistance junction pin (dissipated power = 1 w) 35 c/w r thja thermal resistance junction ambient (dissipated power = 1 w) 80 c/w r thja thermal resistance junction ambient (1) (dissipated power = 1 w) 1. when mounted on a standard single side fr4 board with 150 mm 2 (0.155 sq. in.) of cu (35 m thick). 65 c/w
VIPER37 electrical data doc id 022218 rev 1 7/35 4.3 electrical characteristics (t j = -25 to 125 c, v dd = 14 v (a) ; unless otherwise specified). a. adjust v dd above v ddon startup threshold before setting to 14 v. table 6. power section symbol parameter test condition min. typ. max. unit v bvdss breakdown voltage i drain = 1 ma, v fb = gnd t j = 25 c 800 v i off off state drain current v drain = max. rating, v fb = gnd, t j = 25 c 60 a r ds(on) drain-source on state resistance i drain = 0.4 a, v fb = 3 v, v br = gnd, t j = 25 c 4.5 ? i drain = 0.4 a, v fb = 3 v, v br = gnd, t j = 125 c 9 ? c oss effective (energy related) output capacitance v drain = 0 to 640 v, t j = 25 c 17 pf
electrical data VIPER37 8/35 doc id 022218 rev 1 table 7. supply section symbol parameter test condition min. typ. max. unit voltage v drain _start drain-source start voltage 60 80 100 v i ddch startup charging current v drain = 120 v, v br = gnd, v fb = gnd, v dd = 4 v -2 -3 -4 ma v drain = 120 v, v br = gnd, v fb = gnd, v dd = 4 v after fault. -0.4 -0.6 -0.8 ma v dd operating voltage range after turn-on 8.5 23.5 v v ddclamp v dd clamp voltage i dd = 20 ma 23.5 v v ddon v dd startup threshold v drain = 120 v, v br = gnd, v fb = gnd 13 14 15 v v ddoff v dd undervoltage shutdown threshold 7.5 8 8.5 v v dd(restart) v dd restart voltage threshold v drain = 120 v, v br = gnd, v fb = gnd 44.55 v current i dd0 operating supply current, not switching v fb = gnd, f sw = 0 k h z , v br = gnd, v dd = 10 v 0.9 ma i dd1 operating supply current, switching v drain = 120 v, f sw = 60 khz 2.5 ma v drain = 120 v, f sw = 115 khz 3.5 ma i dd_fault operating supply current, with protection tripping v dd = 10 v 400 a i dd_off operating supply current with v dd < v dd_off v dd = 7 v 270 a
VIPER37 electrical data doc id 022218 rev 1 9/35 table 8. controller section symbol parameter test condition min. typ. max. unit feedback pin v fbolp overload shutdown threshold 4.5 4.8 5.2 v v fblin linear dynamics upper limit 3.2 3.5 3.7 v v fbbm burst mode threshold voltage falling 0.6 v v fbbmhys burst mode hysteresis voltage rising 100 mv i fb feedback sourced current v fb = 0.3 v -150 -200 -280 a 3.3 v < v fb < 4.8 v -3 a r fb(dyn) dynamic resistance v fb < 3.3 v 14 21 k ? h fb ? v fb / ? i d 26v/a cont pin v cont_l low level clamp voltage i cont = -100 a 0.5 v v cont_h high level clamp voltage i cont = 1 ma 5 5.5 6 v current limitation i dlim max. drain current limitation v fb = 4 v, i cont = -10 a t j = 25 c 0.95 1 1.05 a t ss soft-start time 8.5 ms t on_min minimum turn-on time 220 400 480 ns td propagation delay 100 ns t leb leading edge blanking 300 ns i d_bm peak drain current during burst mode v fb = 0.6 v 160 ma oscillator section f osc VIPER37l v dd = operating voltage range, v fb = 1 v 54 60 66 khz VIPER37h 103 115 127 khz fd modulation depth VIPER37l 4 khz VIPER37h 8 khz fm modulation frequency 250 hz d max maximum duty cycle 70 80 %
electrical data VIPER37 10/35 doc id 022218 rev 1 table 8. controller section (continued) symbol parameter test condition min. typ. max. unit overcurrent protection (2 nd ocp) i dmax second overcurrent threshold 1.7 a overvoltage protection v ovp overvoltage protection threshold 2.733.3v t strobe overvoltage protection strobe time 2.2 us brownout protection v brth brownout threshold voltage falling 0.41 0.45 0.49 v v brhyst voltage hysteresis above v brth voltage rising 50 mv i brhyst current hysteresis 7 12 a v brclamp clamp voltage i br = 250 a 3 v v dis brownout disable voltage 50 150 mv thermal shutdown t sd thermal shutdown temperature 150 160 c t hyst thermal shutdown hysteresis 30 c
VIPER37 electrical data doc id 022218 rev 1 11/35 figure 4. minimum turn-on time test circuit figure 5. brownout threshold test circuits figure 6. ovp threshold test circuits note: adjust v dd above v ddon startup threshold before setting to 14 v. 14 v 3 .5 v 50 ? 30 v fb br v(drain) i(drain) i dlim time time t onmin 90 % 10 % gnd cont vdd drain drain drain drain drain 14 v 2 v 10 k ? 30 v fb br gnd cont vdd drain drain drain drain drain v brth +v brhyst v brth v(br) i(br) v dis i brhyst i(drain) time time time i brhyst v ovp v(cont) v(drain) time time 14 v 2 v 10 k ? 30 v fb br gnd cont vdd drain drain drain drain drain
typical electrical characteristics VIPER37 12/35 doc id 022218 rev 1 5 typical electrical characteristics figure 7. current limit vs. t j figure 8. switching frequency vs. t j figure 9. drain start voltage vs. t j figure 10. hfb vs. t j 7->?&@ ,'/,0,'/,0#?& ".w ".w 7->?&@ )26&)26&#?& ".w 7->?&@ 9'5$,1b67$579'5$,1b67$57#?& ".w 7->?&@ +)%+)%#?&
VIPER37 typical electrical characteristics doc id 022218 rev 1 13/35 figure 11. brownout threshold vs. t j figure 12. brownout hysteresis vs. t j ".w 7->?&@ 9%5wk9%5wk#?& ".w 7->?&@ 9%5+\vw9%5+\vw#?& figure 13. brownout hysteresis current vs. t j figure 14. operating supply current (not switching) vs. t j ".w 7->?&@ ,%5+\vw,%5+\vw#?& ".w 7->?&@ ,'',''#?&
typical electrical characteristics VIPER37 14/35 doc id 022218 rev 1 figure 15. operating supply current (switching) vs. t j figure 16. current limit vs. r lim figure 17. power mosfet on resistance vs. t j figure 18. power mosfet breakdown voltage vs. t j ".w 7->?&@ ,'',''#?& ".w 5olp>n2kp@ ,'/,0,'/,0#.2kp ".w 7->?&@ 5'6215'621#?& ".w 7->?&@ 9%9'669%9'66#?&
VIPER37 typical electrical characteristics doc id 022218 rev 1 15/35 figure 19. thermal shutdown 4 * 6 $$ ) $2!). 6 $$o n wlph 6 $$o ff 6 $$2%34!24 4 3$ wlph wlph 4 3$ 7 +<67 6kxwgrzqdiwhuryhuwhpshudwxuh 1rupdorshudwlrq 1rupdorshudwlrq
typical circuit VIPER37 16/35 doc id 022218 rev 1 6 typical circuit figure 20. min-features flyback application figure 21. full-features flyback application opto r5 c6 ac in r3 ac in vout d3 r1 c5 u2 r4 br c4 r6 c3 c1 d1 gnd c2 r2 d2 br cont drain source control vcc fb v dd gnd br cont drain source control vcc fb c3 c2 br vout r2 daux c5 gnd rl r3 rovp rh rlim r6 d2 u2 ac in d3 r1 c6 opto d1 c4 r5 ac in c1 r4 v dd gnd
VIPER37 efficiency performances for a typical flyback converter doc id 022218 rev 1 17/35 7 efficiency performances for a typical flyback converter the efficiency of the converter has been measured in different load and line voltage conditions. in accordance with the energy star ? average active mode testing efficiency method, the efficiency measurements have been performed at 25%, 50% and 75% and 100% of the rated output power, at both 115 v ac and 230 v ac . figure 22. power supply consumption at light output loads, v out =5 v table 9. power supply efficiency, v out = 5 v, v in = 115 v ac %load iout vout pout pin efficiency 25% 0.75 5.04 3.78 4.83 78.26% 50% 1.5 5.04 7.56 9.72 77.78% 75% 2.25 5.04 11.34 14.84 76.42% 100% 3 5.04 15.12 20.04 75.45% average efficiency 76.97% table 10. power supply efficiency, v out = 5 v, v in = 230 v ac %load iout vout pout pin efficiency 25% 0.75 5.04 3.78 5.01 75.45% 50% 1.5 5.04 7.56 9.76 77.46% 75% 2.25 5.04 11.34 14.67 77.30% 100% 3 5.03 15.09 19.59 77.03% average efficiency 76.81% 50 100 150 200 250 300 0 50 100 150 200 250 300 350 200mw 100mw 50mw 30mw input power [mw] input voltage [vac]
efficiency performances for a typical flyback converter VIPER37 18/35 doc id 022218 rev 1 figure 23. power supply consumption at no output load, v out =5 v 50 100 150 200 250 300 10 15 20 25 30 35 40 45 50 55 60 65 no brownout with brownout input power [mw] input voltage [vac]
VIPER37 operation description doc id 022218 rev 1 19/35 8 operation description the device is a high-performance low-voltage pwm controller chip with an 800 v avalanche rugged power section. the controller includes: the oscillator with jittering feature, the startup circuits with soft-start feature, the pwm logic, the current limit circuit with adjustable set point, the second overcurrent circuit, the burst mode management, the brownout circuit, the uvlo circuit, the auto-restart circuit, and the thermal protection circuit. the current limit set-point is set by the cont pin. the burst mode operation guarantees high performance in standby mode and helps to accomplish the energy saving norm. all the fault protections are built in auto-restart mode with very low repetition rate to prevent the ic overheating. 8.1 power section and gate driver the power section is implemented with an avalanche ruggedness n-channel mosfet, which guarantees safe operation within the specified energy rating as well as high dv/dt capability. the power section has a b vdss of 800 v min. and a typical r ds(on) of 4.5 ? at 25 c. the integrated sensefet structure allows a virtually loss-less current sensing. the gate driver is designed to supply a controlled gate current during both turn-on and turn- off in order to minimize common mode emi. under uvlo conditions an internal pull-down circuit holds the gate low in order to ensure that the power section cannot be turned on accidentally. 8.2 high voltage startup generator the hv current generator is supplied through the drain pin and is enabled only if the input bulk capacitor voltage is higher than the v drain_start threshold, 80 v dc (typical). when the hv current generator is on, the i ddch current (3 ma typical value) is delivered to the capacitor on the v dd pin. in the case of auto-restart mode after a fault event, the i ddch current is reduced to 0.6 ma, in order to have a slow duty cycle during the restart phase.
operation description VIPER37 20/35 doc id 022218 rev 1 8.3 power-up and soft-start if the input voltage rises up to the device start threshold v drain_start , the v dd voltage begins to grow due to the i ddch current (see ta b l e 7 ) coming from the internal high voltage startup circuit. if the v dd voltage reaches the v ddon threshold (see ta bl e 7 ), the power mosfet starts switching and the hv current generator is turned off (see figure 25 ). the ic is powered by the energy stored in the capacitor on the v dd pin, c vdd , until the self- supply circuit (typically an auxiliary winding of the transformer and a steering diode) develops a voltage high enough to sustain the operation. the c vdd capacitor must be sized correctly in order to avoid fast discharge and keep the needed voltage value higher than the v ddoff threshold. in fact, a too low capacitance value could terminate the switching operation before the controller receives any energy from the auxiliary winding. the following formula can be used for the v dd capacitor calculation: equation 1 the t ssaux is the time needed for the steady-state of the auxiliary voltage. this time is estimated by the applicator according to the output stage configurations (transformer, output capacitances, etc.). during the converter startup time, the drain current limitation is progressively increased to the maximum value. in this way the stress on the secondary diode is considerably reduced. it also helps to prevent transformer saturation. the soft-start time lasts 8.5 ms and the feature is implemented for every attempt of the startup converter or after a fault. c vdd i ddch t ssaux v ddon v ddoff ? ---------------------------------------- =
VIPER37 operation description doc id 022218 rev 1 21/35 figure 24. i dd current during startup and burst mode figure 25. timing diagram: normal power-up and power-down sequences "5234-/$% ./2-!,-/$% 34!24 50 ./2-!,-/$% ) $$ ch m ! ) $$ ) $$ ) $$ 6 &" bm 6 &" 6 $2!). 6 &" bmhy s 6 &" lin 6 &"o lp 6 $$ 6 $$o ff 6 $$o n t t t t ) $$ 6 $$ 6 $2!). 6 $$o n wlph 6 ). 6 $2!). ? 34! 24 0o wer o n 0o wer o ff 1rupdorshudwlrq uhjxodwlrqlvorvwkhuh 9 ,1 9 '5$,1b67$57 +9vwduwxslvqrpruhdfwlydwhg 6 $$o ff 6 $$2%34!24 ) $$ ch m ! wlph wlph wlph
operation description VIPER37 22/35 doc id 022218 rev 1 figure 26. timing diagram: soft-start 8.4 power down operation at converter power down, the system loses regulation as soon as the input voltage is so low that the peak current limitation is reached. the v dd voltage drops and when it falls below the v ddoff threshold (see ta b l e 7 ) the power mosfet is switched off, the energy transfers to the ic interrupted and consequently the v dd voltages decrease, figure 25 . later, if the v in is lower than v drain_start (see ta b l e 7 ), the startup sequence is inhibited and the power down completed. this feature is useful to prevent the converter?s restart attempts and ensures monotonic output voltage decay during the system power down. 8.5 auto-restart operation if, after a converter power down, the v in is higher than v drain_start, the startup sequence is not inhibited and is activated only when the v dd voltage drops below the v dd(restart) threshold (see ta b l e 7 ). this means that the hv startup current generator restarts the v dd capacitor charging only when the v dd voltage drops below v dd(restart) . the scenario described above is, for instance, a power down because of a fault condition. after a fault condition, the charging current i ddch is 0.6 ma (typ.) instead of the 3 ma (typ.) of a normal startup converter phase. this feature, together with the low v dd(restart) threshold, ensures that, after a fault, the restart attempts of the ic have a very long repetition rate and the converter works safely with extremely low power throughput. figure 27 shows the ic behavior after a short-circuit event. fblin v v fbolp i drain v fb t ss t t i dlim
VIPER37 operation description doc id 022218 rev 1 23/35 figure 27. timing diagram: behavior after short-circuit 8.6 oscillator the switching frequency is internally fixed to 60 khz or 115 khz. in both cases the switching frequency is modulated by approximately 4 khz (60 khz version) or 8 khz (115 khz version) at a 250 hz (typ.) rate, so that the resulting spread-spectrum action distributes the energy of each harmonic of the switching frequency over a number of side- band harmonics having the same energy on the whole but smaller amplitudes. 8.7 current mode conversion with adjustable current limit set point this device is a current mode converter: the drain current is sensed and converted into voltage that is applied to the non-inverting pin of the pwm comparator. this voltage is compared with the one on the feedback pin through a voltage divider on a cycle-by-cycle basis. the device has a default current limit value, i dlim , that the user can adjust according to the electrical specifications, through the r lim resistor connected to the cont pin (see figure 16 ). the cont pin has a minimum current sunk, needed to activate the i dlim adjustment: without r lim or with high r lim (i.e. 100 k ? ), the current limit is fixed to the default value (see i dlim , ta b l e 8 ). ) $$ 6 $$ 6 $3 6 $$o n wlph 6kruwflufxlwrffxuvkhuh 6 $$o ff 6 $$2%34!24 ) $$ ch m ! wlph wlph wlph 6 &" 6 &"o lp 6 &" lin 7 5(3(7,7,21 [7 5(3(7,7,21
operation description VIPER37 24/35 doc id 022218 rev 1 8.8 overvoltage protection (ovp) the device can monitor the converter output voltage. this operation is done by the cont pin during power mosfet off-time, when the voltage generated by the auxiliary winding tracks the converter's output voltage, through turn ratio (see figure 28 ). in order to perform the output voltage monitor, the cont pin must be connected to the aux. winding through a resistor divider made up of r lim and r ovp (see figure 21 or figure 29 ). if the voltage applied to the cont pin exceeds the internal reference v ovp (see ta b l e 8 ) for four consecutive times, the controller recognizes an overvoltage condition. this special feature uses an internal counter; that is to reduce sensitivity to noise and prevent the latch from being erroneously activated (see figure 28 ). the counter is reset every time the ovp signal is not triggered in one oscillator cycle. referring to figure 21 , the resistors? divider ratio k ovp is given by: equation 2 equation 3 where: v ovp is the ovp threshold (see ta b l e 8 ) v out ovp is the converter output voltage value to activate the ovp set by the user n aux is the auxiliary winding turns n sec is the secondary winding turns v dsec is the secondary diode forward voltage v daux is the auxiliary diode forward voltage r ovp together with r lim make up the output voltage divider. then, once the r lim value is fixed , according to the desired i dlim , the r ovp can be calculated by: equation 4 n aux n sec -------------- k ovp v ovp n aux n sec -------------- v outovp v dsec + () v daux ? ? ----------------------------------------------------------------------------------------------------- = k ovp r lim r lim r ovp + ---------------------------------- = r ovp r lim 1k ovp ? k ovp ---------------------- - =
VIPER37 operation description doc id 022218 rev 1 25/35 the resistor values are such that the current sourced and sunk by the cont pin are within the rated capability of the internal clamp. figure 28. ovp timing diagram 8.9 about the cont pin referring to figure 29 , the features below can be implemented through the cont pin: 1. current limit set point 2. overvoltage protection on the converter output voltage ta b l e 1 1 , referring to figure 29 , lists the external resistance combinations needed to activate one or more of the cont pin functions. figure 29. cont pin configuration t v d s va u x t t t s trobe t counter re s et t counter s tatu s t 0 cont (pin 4) sampling time ovp fault 0 0 0 0 1 1 2 2 0 0 1 1 2 2 3 3 4 0 e r u l i a f p o o l k c a b d e e f e c n a b r u t s i d y r a r o p m e t n o i t a r e p o l a m r o n t v d s t t t s trobe t counter re s et t counter s tatu s t 0 (pin 4) ovp fault 0 0 0 0 1 2 0 1 2 3 0 e r u l i a f p o o l k c a b d e e f e c n a b r u t s i d y r a r o p m e t n o i t a r e p o l a m r o n t v ovp t s trobe + - current limit comparator to ovp protection r ovp r lim d aux soft start cont from sensefet auxiliary winding to pw m logic ovp detection logic curr. lim. block ocp
operation description VIPER37 26/35 doc id 022218 rev 1 8.10 feedback and overload protection (olp) the device is a current mode converter: the feedback pin controls the pwm operation, controls the burst mode, and actives the overload protection. figure 30 and figure 31 show the internal current mode structure. with the feedback pin voltage between v fbbm and v fblin , (see ta b l e 8 ) the drain current is sensed and converted into voltage that is applied to the non-inverting pin of the pwm comparator. this voltage is compared with the one on the feedback pin through a voltage divider on a cycle-by-cycle basis. when these two voltages are equal, the pwm logic orders the switch- off of the power mosfet. the drain current is always limited to the i dlim value. in case of overload, the feedback pin increases in reaction to this event and when it goes higher than v fblin , the pwm comparator is disabled and the drain current is limited to i dlim by the ocp comparator, see figure 2 . when the feedback pin voltage reaches the threshold v fblin , an internal current generator starts to charge the feedback capacitor (c fb ) and when the feedback voltage reaches the v fbolp threshold, the converter is turned off and the startup phase is activated with a reduced value of i ddch to 0.6 ma, see ta b l e 7 . during the first startup phase of the converter, after the soft-start time (t ss ), the output voltage may force the feedback pin voltage to rise up to the v fbolp threshold that switches off the converter itself. to avoid this event, the appropriate feedback network must be selected according to the output load. moreover, the feedback network fixes the compensation loop stability. figure 30 and figure 31 show the two different feedback networks. the time from the overload detection (vfb = v fblin ) to the device shutdown (vfb = v fbolp ) can be set by the c fb value (see figure 30 and figure 31 ), using the formula: equation 5 where i fb is the value, reported in ta b l e 8 , when the fb voltage is between v fblin and v fbolp . in figure 30 , the capacitor connected to the fb pin (c fb ) is part of the compensation circuit as well as being necessary to activate the overload protection. table 11. cont pin configurations function / component r lim (1) 1. r lim must be fixed before r ovp . r ovp d aux i dlim reduction see figure 16 no no ovp 80 k ? see equation 4 ye s i dlim reduction + ovp see figure 16 see equation 4 ye s t olp delay ? c fb v fbolp v fblin ? i fb --------------------------------------- - =
VIPER37 operation description doc id 022218 rev 1 27/35 after the startup time, t ss , during which the feedback voltage is fixed at v fblin , the output capacitor may not be at its nominal value and the controller interprets this situation as an overload condition. in this case, the olp delay helps to avoid an incorrect device shutdown during the startup phase. owing to the above considerations, the olp delay time must be long enough to bypass the initial output voltage transient and check the overload condition only when the output voltage is in steady-state. the output transient time depends on the value of the output capacitor and on the load. when the value of the c fb capacitor calculated for the loop stability is too low and cannot ensure enough olp delay, an alternative compensation network can be used, shown in figure 31 . using this alternative compensation network, two poles (f pfb , f pfb1 ) and one zero (f zfb ) are introduced by the capacitors c fb and c fb1 and the resistor r fb1 . the capacitor c fb introduces a pole (f pfb ) at a higher frequency than f zb and f pfb1 . this pole is usually used to compensate the high frequency zero due to the esr (equivalent series resistor) of the output capacitance of the flyback converter. the mathematical expressions of these poles and zero frequency, considering the scheme in figure 31 , are reported by the equations below: equation 6 equation 7 equation 8 r fb(dyn) is the dynamic resistance seen by the fb pin. the c fb1 capacitor fixes the olp delay and usually c fb1 results much higher than c fb . equation 5 can still be used to calculate the olp delay time but c fb1 must be considered instead of c fb . using the alternative compensation network, the user can satisfy, in all cases, the loop stability and the correct olp delay time alike. 1 fb 1 fb zfb r c 2 1 f ? ? ? = () 1 fb ) dyn ( fb fb 1 fb ) dyn ( fb pfb r r c 2 r r f ? ? ? ? + = () ) dyn ( fb 1 fb 1 fb 1 pfb r r c 2 1 f + ? ? ? =
operation description VIPER37 28/35 doc id 022218 rev 1 figure 30. fb pin configuration 1 figure 31. fb pin configuration 2 8.11 burst mode operation at no load or very light load when the load decreases, the feedback loop reacts by lowering the feedback pin voltage. if it falls below the burst mode threshold, v fbbm , the power mosfet is no longer allowed to be switched on. after the mosfet stops, as a result of the feedback reaction to the energy delivery stop, the feedback pin voltage increases and when it exceeds the level, v fbbm + v fbbmhys , the power mosfet starts switching again. the burst mode thresholds are reported in ta b l e 8 and figure 32 shows this behavior. depending on the output load, the power alternates between periods of time in which the power mosfet is switching and is enabled, with periods of time when the power mosfet is not switching; this working mode is called burst mode. the power delivered to the output during switching periods exceeds the load power demands; the excess of power is balanced from the non-switching period where no power is processed. the advantage of burst mode operation is an average switching frequency much lower then the normal operation working frequency, up to a few hundred hertz, minimizing all frequency related losses. during burst mode the drain current peak is clamped to the level, i d_bm , reported in ta b l e 8 . from sense fet 4.8v burst pwm control cfb to pwm logic burst-mode references burst-mode logic + - pwm + - olp comparator to disable logic 4.8v from sense fet pwm control + - pwm burst to disable logic + - olp comparator to pwm logic burst-mode logic cfb1 rfb1 cfb burst-mode references
VIPER37 operation description doc id 022218 rev 1 29/35 figure 32. burst mode timing diagram, light load management 8.12 brownout protection brownout protection is a not-latched shutdown function activated when a condition of mains undervoltage is detected. the brownout comparator is internally referenced to v brth , ta b l e 8 , and disables the pwm if the voltage applied at the br pin is below this internal reference. under this condition the power mosfet is turned off. until the brownout condition is present, the vdd voltage continuously oscillates between the v ddon and the uvlo thresholds, as shown in the timing diagram of figure 33 . a voltage hysteresis is present to improve the noise immunity. the switching operation is restarted as the voltage on the pin is above the reference plus the previously mentioned voltage hysteresis, see figure 5 . the brownout comparator is provided also with a current hysteresis, i brhyst . the user must set the rectified input voltage above which the power mosfet starts switching after brownout event, v inon , and the rectified input voltage below which the power mosfet is switched off, v inoff . thanks to the i brhyst , see ta b l e 8 , these two thresholds can be set separately. time time time 9 &203 9 )%ep 9 )%epk\v 9 )%ep , '' , '' , '' , '5$,1 , 'b%0 %xuvw0rgh
operation description VIPER37 30/35 doc id 022218 rev 1 when the v inon and the v inoff levels are fixed, with reference to figure 33 , the following relationships can be established for the calculation of the resistors r h and r l : equation 9 equation 10 for a proper operation of this function, v in on must be less than the peak voltage at minimum mains and v in off less than the minimum voltage on the input bulk capacitor at minimum mains and maximum load. the br pin is a high impedance input connected to high value resistors, it is therefore prone to pick up noise, which might alter the off threshold when the converter operates or creates an undesired switch-off of the device during esd tests. it is possible to bypass the pin to ground with a small film capacitor (e.g. 1-10 nf) to prevent any malfunctioning of this kind. if the brownout function is not used, the br pin must be connected to gnd, ensuring that the voltage is lower than the minimum v dis threshold (50 mv), see ta b l e 8 . figure 33. brownout protection: br external setting and timing diagram 'lvdeoh & %5 9 ',6 9 lqb2. 9 %5wk 5 + , %5k\vw 5 / 9 ,1b'& 9'' 6 /54 6 ). 6 ).o n 6 ).o ff 6 $2!). ? 34!24 6 "2 6 in? /+ ) "2 6 "2 th ) "2 hyst 6 $$ 6 $$o n 6 $$o ff 6 $3 6 $$2%34!24 brhyst brth brth inoff brhyst inoff inon brhyst brhyst l i v v v v v v i v r ? ? ? + ? = brhyst brhyst l l brhyst brhyst inoff inon h i v r r i v v v r + ? ? =
VIPER37 operation description doc id 022218 rev 1 31/35 in order to enable the brownout function, the br pin voltage must be higher than the maximum v dis threshold (150 mv), see ta b l e 8 . 8.13 2 nd level overcurrent protection and hiccup mode the device is protected against short-circuit of the secondary rectifier, short-circuit on the secondary winding, or a hard-saturation of the flyback transformer. such an anomalous condition is invoked when the drain current exceeds the threshold i dmax (see ta b l e 8 ). to distinguish a real malfunction from a disturbance (e.g. induced during esd tests) a ?warning state? is entered after the first signal trip. if, in the subsequent switching cycle, the signal is not tripped, a temporary disturbance is assumed and the protection logic is reset in its idle state; otherwise, if the i dmax threshold is exceeded for two consecutive switching cycles, a real malfunction is assumed and the power mosfet is turned off. the shutdown condition is latched as long as the device is supplied. while it is disabled, no energy is transferred from the auxiliary winding; hence the voltage on the v dd capacitor decays to the v dd undervoltage threshold (v ddoff ), which clears the latch. the startup hv current generator is still off, until the v dd voltage goes below its restart voltage, v dd(restart) . after this condition the v dd capacitor is charged again by a 600 a current, and the converter switching restarts if the v ddon occurs. if the fault condition is not removed the device enters auto-restart mode. this behavior results in a low-frequency intermittent operation (hiccup-mode operation), with very low stress on the power circuit. see the timing diagram of figure 34 . figure 34. timing diagram: hiccup-mode ocp v drain v dd i drain v ddon time v ddof f v dd(re s tart) time time hiccup-mode secondary diode short circuit normal operation i dmax
package mechanical data VIPER37 32/35 doc id 022218 rev 1 9 package mechanical data in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack specifications, grade definitions and product status are available at: www.st.com . ecopack is an st trademark. table 12. sdip10 mechanical data dim. mm min. typ. max. a 5.33 a1 0.38 a2 2.92 4.95 b 0.36 0.56 b2 0.51 1.15 c 0.2 0.36 d 9.02 10.16 e 7.62 8.26 e1 6.1 7.11 e2 7.62 e3 10.92 e 1.77 l 2.92 3.81
VIPER37 package mechanical data doc id 022218 rev 1 33/35 figure 35. sdip10 mechanical drawing
revision history VIPER37 34/35 doc id 022218 rev 1 10 revision history table 13. document revision history date revision changes 17-feb-2012 1 initial release
VIPER37 doc id 022218 rev 1 35/35 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a particular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. unless expressly approved in writing by two authorized st representatives, st products are not recommended, authorized or warranted for use in military, air craft, space, life saving, or life sustaining applications, nor in products or systems where failure or malfunction may result in personal injury, death, or severe property or environmental damage. st products which are not specified as "automotive grade" may only be used in automotive applications at user?s own risk. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or register ed trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2012 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - philippines - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

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